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19-1166; Rev 0; 12/96
Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA
_______________General Description
The MAX1101 is a highly integrated IC designed primarily for digitizing the output of a linear CCD array. It provides the components required for all necessary analog functions, including clamp circuitry for blacklevel correction or correlated double sampling (CDS), a three-input multiplexer (mux), and an 8-bit analog-todigital converter (ADC). The MAX1101 operates with a sample rate up to 1MHz and with a wide range of linear CCDs. The logic interface is serial, and a single input sets the bidirectional data line as either data in or data out, thus minimizing the I/O pins required for communication. Packaged in a 24-pin SO, the MAX1101 is available in the commercial (0C to +70C) temperature range.
____________________________Features
o 1.0 Million Pixels/sec Conversion Rate o Built-In Clamp Circuitry for Black-Level Correction or Correlated Double Sampling o 64-Step PGA, Programmable from Gain = -2 to -10 o Auxiliary Mux Inputs for Added Versatility o Compatible with a Large Range of CCDs o 8-Bit ADC Included o Space-Saving, 24-Pin SO Package
MAX1101
________________________Applications
Scanners Fax Machines Digital Copiers CCD Imaging
______________Ordering Information
PART MAX1101CWG TEMP. RANGE 0C to +70C PIN-PACKAGE 24 Wide SO
Pin Configuration appears on last page.
___________________________________________________Typical Operating Circuit
CEXT 0.047F
1 2 3
GND CCDIN GND AIN1 GND AIN2 GND
GND
24 23 22 21 20 19 18 17 16 P/C/ STATE LOGIC 0.1F +5V DC (SUPPLY)
MAX1101
VDD CLAMP
CCD ARRAY
4 5 6 7
VIDSAMP LOAD DATA SCLK MODE GND
VDD 15 11 0.1F 12 AUXILIARY ANALOG INPUTS 12 REFGND REFREFBIAS REF+ 14 13 0.1F +5V DC (REFERENCE)
________________________________________________________________ Maxim Integrated Products
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................................-0.3V to +12V All Pins to GND...........................................-0.3V to (VDD + 0.3V) Current into Every Pin (except VDD) .................................20mA Current into VDD ...............................................................50mA Continuous Power Dissipation (TA = +70C) SO (derate 11.76mW/C above +70C) ......................941mW Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VREFBIAS = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1F, CEXT = 47nF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Resolution Differential Nonlinearity Integral Nonlinearity Total Unadjusted Error Zero-Scale Drift Full-Scale Drift Maximum Sample Rate Minimum Sample Rate Input Full-Power Bandwidth Aperture Delay ANALOG INPUT--CCD INTERFACE Maximum Peak CCD Differential Signal Range Minimum PGA Gain Setting Maximum PGA Gain Setting Gain Adjust Resolution Gain Adjust Step Size PGA Gain Error Black Sample Switch On-Resistance RON(BSS) Input Leakage (Note 2) CCD Interface Offset Voltage IL(CCDIN) VOS(CCD) Including black sample switch off-leakage VVIDEO = VRESET (Figure 4) 0 VWHITE VWHITE = (VREF+ - VREF-) / GPGA GPGA = -2 GPGA = -10 -1.9 -9.375 1.25 0.25 -2 -9.875 64 0.125 5 60 1 4 150 50 8 -2.1 -10.375 V V/V V/V Steps V/V % Gain nA LSB tAP SYMBOL N DNL INL TUE TCVOS TCFS fs (Note 1) VIN = 2.5Vp-p 0.67 1 1 10 125 0.016 1.2 No-missing-codes guaranteed Best straight-line fit CONDITIONS MIN 8 0.5 1 1 1.5 2.5 TYP MAX UNITS Bits LSB LSB LSB %V/C %FS/C MHz kHz MHz ns
ANALOG-TO-DIGITAL CONVERTER
ANALOG INPUT--AUXILIARY INPUTS Input Voltage Range Input Capacitance (Note 1) On-Resistance VIN CIN(ON) CIN(OFF) RON Channel on Channel off 120 VREFVREF+ 45 10 V pF
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VREFBIAS = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1F, CEXT = 47nF, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER REFERENCE VOLTAGE INPUT Positive Reference Voltage Negative Reference Voltage POWER SUPPLIES Positive Supply-Voltage Range PSRR, PGA and ADC Supply Current DIGITAL INPUTS/OUTPUTS Digital Input Voltage High Digital Input Voltage Low Digital Input Leakage Current Digital Output Voltage High Digital Output Voltage Low Digital Output Leakage Current SCLK Frequency SCLK Pulse Width VIDSAMP Pulse Width VIDSAMP to CLAMP Separation LOAD Pulse Width VIDSAMP Fall to SCLK Rise Time VIDSAMP Fall to DATA VIDSAMP to Reset Separation Reset to CLAMP Separation SCLK Rise to DATA DATA Set-Up Time DATA Hold Time LOAD Fall to SCLK Rise Time SCLK Rise to LOAD Rise Time MODE Setup Time CLAMP Pulse Width CLAMP Fall to Video Update Digital Quiet Time (Note 3) VIH VIL IIL VOH VOL IOL fSCLK tSPW tVS tVB tLD tVLS tVLD tVR tRB tSD tDSU tDH tLS tSL tMSU tBS tBC tQ (Note 1) around VIDSAMP falling edge MODE = 0 MODE = 0 Same as bus-relinquish time 20 20 50 50 50 300 20 20 MODE = 1 MODE = 1 (Note 2) (Note 2) 50 50 60 50 500 50 50 50 60 ISOURCE = 4mA ISINK = 4mA Output in high-impedance mode -10 -10 VDD - 0.5 0.5 10 10 3.5 1.5 10 V V A V V A MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD PSRR IDD 4.75V VDD 5.25V 4.75 48 5 60 20 40 5.25 V dB mA VREF+ VREFInternally generated, VREFBIAS = 5V Internally generated, VREFBIAS = 5V 2.94 0.49 3.00 0.50 3.06 0.51 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1101
DIGITAL TIMING SPECIFICATIONS (tr , tf 10ns, CL 50pF, unless otherwise noted)
Note 1: Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as performance may degrade, particularly at high temperatures. Note 2: Production test equipment settling time prohibits leakage measurements below 1nA. Lab equipment has shown the MAX1101 switch input leakage below 1pA at TA = +25C, and below 50pA at TA = +70C. Note 3: Not a test parameter. Recommended for optimal performance.
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
______________________________________________________________Pin Description
PIN 1, 3, 5, 7, 10, 16, 24 2 4 6 8, 9, 10 11 12 13 14 15, 23 17 18 19 20 21 22 NAME GND CCDIN AIN1 AIN2 I.C. REFGND REFREF+ REFBIAS VDD MODE SCLK DATA LOAD VIDSAMP CLAMP Ground CCD Input. Connect CCD through a series 0.047F capacitor (CEXT). Auxiliary Analog Input Channel 1 Auxiliary Analog Input Channel 2 Internally Connected. Do not connect to this pin. Reference Ground. Ground reference for all analog signals. Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND REF- REF+. Nominally 0.5V. Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF- REF+ VDD. Nominally 3.0V. Reference Power Supply. Connect to external +5.0V to set VREF+ to +3.0V and VREF- to +0.5V. Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together, close to the MAX1101. Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the PGA and mux. Serial Clock Input Data Input or Output, as controlled by MODE Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0. Control Input. Samples the video level and initiates the ADC conversion. Control Input. Samples black level. Can be used for correlated double sampling. FUNCTION
REFBIAS AIN2 AIN1 2 1 MUX CCDIN CLAMP CLAMP CIRCUIT PGA GAIN 6 0 2 ADC 8 REF-
_______________Detailed Description
Overview
The MAX1101 directly processes the pixel stream from a monochrome CCD, and removes black level, offset, and noise errors through an internal clamp circuit, which can be used as a correlated double sampler (CDS). It uses a 6-bit, programmable-gain amplifier (PGA) to adjust gain. A three-input multiplexer (mux) selects either the PGA output or two unassigned inputs (AIN1, AIN2). The processed analog signal is digitized by an 8-bit, half-flash analog-to-digital converter (ADC), and output serially through the DATA pin. Digital data is input and output through the bidirectional serial pin (DATA) synchronously with the external serial clock (SCLK). When MODE = 0, the mux channels and the PGA gain can be programmed via DATA. With MODE = 1 (high), ADC serial data is output through this pin.
REF+
REFGND
VIDSAMP REGISTER 6 REGISTER 2
REGISTER 8 DATA SCLK LOAD MODE
SERIAL PORT
Figure 1. MAX1101 Functional Diagram
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
REF+ REF+ REFS1 CF CLAMP S1 S1P FROM CCD CEXT 0.047F S2 CI TO ADC REFREFVIDSAMP S1* S2* S1P* ON OFF OFF ON OFF ON * INTERNALLY GENERATED SIGNALS VREF+ - VVIDEO (FROM DC RESTORE) CI VOUT = VREF- V0S S2 CI CF REF+ REF-
Figure 3a. PGA Connection with VIDSAMP = Low
CF
REF-
Figure 2. PGA Functional Diagram
Figure 3b. PGA Connection with VIDSAMP = High
Programmable-Gain Amplifier
The PGA amplifies the differential video signal from the CCD (at CCDIN). Gain is settable with the 6-bit control word from -2 to -10 in 64 steps, in increments of -0.125. The PGA also provides for periodic DC restoration of the capacitively coupled input. As shown in Figure 2, the switched-capacitor amplifier's gain is set by the ratio CI/CF. The input is sampled on the CI capacitors, which is a set of equal capacitors. The 6-bit gain control word determines the number of capacitors used. Thus the PGA gain is set from -2 to -10. A voltage equal to VREF- is applied to the PGA's noninverting input. This offsets the PGA output to be within the range of the ADC (VREF- to VREF+).
VIDSAMP controls the sampling of the video signal and offset nulling of the PGA. To null out the offset, VIDSAMP causes switches S1 and S1P to close, placing the amplifier in a unity-gain configuration, as shown in Figure 3a. This configuration causes the amplifier's offset voltage to be stored on CF. In the next portion of the cycle, when VIDSAMP returns low, the S1 switches are opened and S2 is closed (Figure 3b). This is the standard inverting op-amp configuration. The only difference is that capacitors are used to set the gain, and the amplifier's offset voltage has been stored on these capacitors and is thus canceled. The amplifier's output is [CF/CI] x VVIDEO + VREF-. The CDS function is shown in Figure 4.
ADC
The ADC uses a recycling half-flash conversion technique in which a 4-bit flash ADC section achieves an 8-bit result in two steps (Figure 5). Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder (using REF+ and REF-) and provides the upper four data bits. An internal digital-to-analog converter (DAC) uses the four most significant bits (MSBs) to generate the analog result from the first flash conversion and a residue voltage that is the difference between the unknown voltage
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Clamp Circuit
As shown in Figure 2, the CCD output is connected to the MAX1101 input (CCDIN) through an external capacitor, which removes the potentially large DC common-mode voltages from the input signal. Whenever CLAMP is high, the CLAMP switch is closed and C EXT is charged to V REF+ . It can be actuated either once per pixel (sampling reset level) or less frequently (such as for restoring optical black level once per line), as required by the application.
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
CCD OUTPUT LEVELS VARY DUE TO CCD RESET NOISE
CCD OUTPUT
CLAMP PULSE (CLAMP)
CLAMP OUTPUT
VVIDEO
VOLTAGE OF RESET SECTION IS SET TO VREF+ BY CLAMP
SAMPLE-AND-HOLD PULSE (VIDSAMP)
Figure 4. Correlated Double Sampler (CDS)
and the DAC output. The residue is then compared again with the flash comparators to obtain the lower four data bits. Single-shot timers control the timing of the two conversion steps. Once both MSBs and LSBs have been determined, the comparators return to input-acquisition/auto-zero mode.
REF+ REFFROM MUX 4-BIT FLASH ADC
REF+ and REFThe REF+ and REF- pins set the ADC's full-scale range. The optimum input range is +0.5V to +3.0V. Figure 6 shows a matched resistive ladder that generates the reference voltages. Four pins are available: REF+, REF-, REFBIAS, and REFGND. If 5.00V is applied to REFBIAS while REFGND is grounded, then 3.00V and 0.50V are generated at REF+ and REF-, respectively. For increased accuracy or power-supply immunity, REF+ can be connected to an external +3.00V reference. If this is done, the accuracy must be better than 5%. REFBIAS should be left open in this case.
4-BIT DAC OUTPUT REGISTER DATA OUT
VREF+ 16
4-BIT FLASH ADC (4LSB)
Multiplexer
The mux selects either the output of the PGA or one of two other inputs to the ADC. The mux switching is break-before-make to prevent transient shorts between channels. The first two bits of the input control byte select the mux input channel (Table 1).
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Figure 5. ADC Functional Diagram
Serial-Interface Logic
The serial interface inputs and outputs data in 8-bit words. The interface is controlled by four signals: MODE, LOAD, DATA, and SCLK.
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA
MODE MODE controls the direction of data transfer. When MODE = 0, data is being shifted into the MAX1101 at the DATA pin either for the mux or the PGA. When MODE = 1, the ADC output is shifted out from the MAX1101 at the DATA pin. Data is shifted in and out of the MAX1101 at the rising edge of SCLK. LOAD LOAD is normally low and used only when MODE = 0. Once all eight bits have been clocked in, bring LOAD high to update the MAX1101 registers. DATA DATA is a bidirectional I/O pin. MODE controls the direction of data transfer. When MODE = 1, DATA is configured as an output from the shift register. Data is clocked out of the shift register by SCLK's rising edge. When MODE = 0, DATA is configured as an input to the shift register, shifted in by the rising edge of SCLK. In this mode, the DATA output driver is disabled, putting DATA into a high-impedance state and allowing it to be driven externally.
REFBIAS 800 REF+ 1k REF200 REFGND
Data Output Data is clocked in and out of the device with the rising edge of SCLK. The first bit (the MSB, D7) immediately follows the falling edge of VIDSAMP (Figures 7 and 8). The first rising edge of SCLK clocks out the next bit, D6. Data is loaded into the shift register at the falling edge of VIDSAMP. Following the output of D0, DATA output is unspecified for additional SCLK pulses. Eight-bit-wide storage and output registers hold data from the ADC and delay the data output. The timing diagram in Figure 9 shows the data latency of two VIDSAMP cycles. New data is available after the second falling edge of VIDSAMP. Data Input During data input, the first two bits (A0, A1) are the address, selecting either the mux or PGA. The next six bits set the input channel or PGA gain (Table 1). CLAMP and VIDSAMP The last two digital inputs are VIDSAMP and CLAMP. VIDSAMP controls the overall cycle timing, with one VIDSAMP cycle corresponding to one CCD pixel. The input is sampled into the ADC by the falling edge of VIDSAMP. CLAMP controls the black sample switch, which sets a reference DC voltage level (VREF+) at the capacitively coupled CCDIN input. The sample switch is on when CLAMP is high. Control and Interface Logic The control and interface logic consists of a serial I/O port, which shifts data into and out of the MAX1101, and two registers for storing the mux channel and the PGA gain data.
MAX1101
Figure 6. Reference Resistor String
Table 1. Control-Byte Format
FUNCTION Address Analog Input Mux Address CCD PGA No Operation Select CCD input Select AIN1 Select AIN2 Set PGA Gain to -2 Set PGA Gain to -2.125 Set PGA Gain to -9.750 Set PGA Gain to -9.875
X = Don't Care
A0 0 0 1 0 0 0 0 0 0 0
A1 0 1 X 0 0 0 1 1 1 1
D5 MSB -- -- X 0 0 1 0 0 1 1
D4 -- -- X 0 1 0 0 0 1 1
D3 -- -- X 0 0 0 0 0 1 1
D2 -- -- X X X X 0 0 1 1
D1 -- -- X X X X 0 0 1 1
D0 LSB -- -- X X X X 0 1 0 1
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
MODE tMSU SCLK tSL tLD LOAD tDSU DATA A0 A1 tDH D5 D4 D3 D2 D1 D0 tLS tSPW tSPW
Figure 7. MODE = 0 Timing
RESET FEEDTHROUGH CCD OUT tVR tCPW VIDSAMP tQ tVB CLAMP SCLK DATA tVLS tVLD D7 D6 tSD D5 D4 D3 D2 D1 D0 DATA OUTPUT AFTER D0 IS UNSPECIFIED tBS tRB tVS tBC tVB PRECHARGE LEVEL VIDEO LEVEL
Figure 8. MODE = 1 Timing
LOAD controls the loading of data into the internal storage registers during data input. Once all eight input bits have been clocked into the shift register, a rising edge on LOAD clocks the data into the appropriate storage register (mux or PGA), decoded from the first two input bits. The logic is divided into four blocks: the two storage registers, the serial I/O port, and a power-on reset generator. The registers are reset by the power-on reset to place them in a predictable state (input channel = CCD, PGA gain = -2) on power-up. The power-on reset typically has a 2.1s pulse width. The serial I/O port consists of a shift register, an 8-bit storage register, decode logic to clock input data into the appropriate storage register, and an output driver. The 8-bit storage register takes input data from the ADC.
Input Buffers and Output Drivers The DATA driver is capable of driving 50pF load capacitance while meeting the output delay specifications given in the Electrical Characteristics. The gates of the Pchannel and N-channel drivers are driven separately. If MODE is low, both drivers are off and the output is high impedance.
The VIDSAMP, CLAMP, SCLK, and LOAD inputs are buffered and have hysteresis to reject noise with slowslewing signal edges.
__________Applications Information
MAX1101 Timing
Figure 7 shows the timing configuration when MODE = 0 and data is loaded into the MAX1101. Figure 8 shows timing when MODE = 1 and the CCD signal is digitized. Figure 9 is an expansion of Figure 8, illustrating the two-VIDSAMP-cycle data latency. Figure 10 shows the relationship of CLAMP to VIDSAMP when MODE = 1.
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
CCD (OUT)
VIDEO N VIDEO N+1 VIDEO N+2 VIDEO N+3
VIDSAMP CLAMP PGA ADC ADC REG SHIFT REG SCLK DATA
D7 D6 D5 D4 D3 D2 DATA N-3 D1 D0 D7 D6 D5 D4 D3 D2 DATA N-2 D1 D0 D7 D6 D5 D4 D3 D2 DATA N-1 D1 D0 D7 D6 D5 D4 D3 D2 DATA N D1 D0 D7 AUTO-ZERO SAMPLE N AUTO-ZERO SAMPLE N+1 AUTO-ZERO SAMPLE N+2 AUTO-ZERO SAMPLE N+3
MSB N-1
LSB N-1 DATA N-2 DATA N-3
SAMPLE N
MSB N
LSB N DATA N-1 DATA N-2
SAMPLE N+1
MSB N+1
LSB N+1 DATA N DATA N-1
SAMPLE N+2
MSB N+2
LSB N+2 DATA N+1 DATA N
SAMPLE N+3
Figure 9. MODE = 1 Timing Showing Data Latency
BLACK CELL CCD (OUT)
BLACK CELL VIDEO N
VIDSAMP CLAMP (ONCE PER LINE) CLAMP (ONCE PER CELL)
Figure 10. MODE = 1 Timing Showing Relationship of CLAMP to VIDSAMP
Input/Output Transfer Function
CCD Input Figure 11 shows the MAX1101 transfer function for CCDIN. Coding is binary, with a -4LSB offset added to ensure that offsets within the MAX1101, which can be positive or negative, do not cause the ADC to be out of range. Full-scale input range at CCDIN is: (VREF+ - VREF-) / GPGA where G PGA is the gain of the programmable gain amplifier.
Analog Inputs (AIN_) The transfer function for auxiliary inputs is shown in Figure 11. Again, coding is binary and full-scale range is VREF- to VREF+. An offset has not been added to these channels; however, code transitions occur at the 1/2LSB point, as shown in Figure 12.
Implementing Correlated Double Sampling (CDS) or Black-Level Compensation
The CLAMP circuit in the MAX1101 can be used to either accomplish CDS or to compensate for the CCD black level. To accomplish CDS, CLAMP is activated once per
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
pixel during the CCD output waveform's reset phase. To compensate for the CCD black level, CLAMP is activated during the black-pixel portion of the linear array, as shown in Figure 10. Each of these modes requires a different value of CEXT, as described in the following section.
DIGITAL OUTPUT
11. . .111 11. . .110 11. . .101
Choosing CEXT for CDS In CDS applications, CEXT = 4nF. This value is the best compromise to minimize errors due to the CLAMP switch resistance/CEXT time constant and switch charge injection. The following equation represents the error due to incomplete charging of CEXT during integration time: = VRESET x e-t/RC
where VRESET = the maximum change in reset level from one pixel to the next, t = CLAMP pulse width, and R = CLAMP switch resistance (150max). At a sample rate of 670kHz, with t = 750nsec, a 4nF capacitor removes at least 70% of the change in reset voltage level. Typically, R = 60, which corresponds to a 96% cancellation of the change in reset level. The offset due to switch charge injection is represented by 13pC / 4nF = 3mV. Note that this error will behave like any DC offset; that is, it will be constant from pixel to pixel.
100. . .000
00. . .111 00. . .110 00. . .101 00. . .100 00. . .011 00. . .010 00. . .001 00. . .000 -1 V 1V 3V -3 V FS FS FS FS 256 256 256 256 -4 V -2 V 2V FS FS FS 256 256 256 124 V FS 256 VVIDEO 249 V 251 V FS FS 256 256 250 V FS 256
VFS =
VREF+ - VREFGPGA
VVIDEO = VOLTAGE DIFFERENCE BETWEEN THE VIDEO LEVEL AND THE PRE-CHARGE (RESET) LEVEL.
Choosing CEXT in Black-Level Compensation In activating CLAMP once per line to compensate for the CCD black level, the recommended value of CEXT is governed by the following equations:
CEXT 12nF and CEXT N x t x 760pF/sec where N is the number of light-shielded cells, and t is the width of the CLAMP pulse in sec. The second equation ensures that the time constant formed by R x CEXT is small enough that the black level is captured to within 0.5mV during the dark pixel phase. For example, in an array with 27 dark pixels at a 670kHz sample rate, with t = 750nsec, the second equation becomes CEXT 15nF. Capacitors smaller than 12nF can be used; however, offset increases due to switch charge injection, as explained in the section Choosing CEXT for CDS.
Figure 11. Transfer Function for CCDIN
DIGITAL OUTPUT
111. . . . 111 111. . . . 110 111. . . . 101
100. . . 000
000. . . 011 000. . . 010 000. . . 001 000. . . 000 1V 3V FS FS 256 256 2V 4V FS FS VREF256 256 VFS = VREF+ - VREFVAIN_ 253 V 255 V FS FS 256 256 254 V FS 256
Figure 12. Transfer Function for AIN
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Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA
__________________Pin Configuration
MAX1101-FIG13
MAX1101
100.00
TOP VIEW
10.00 ERROR (BITS) GND 1 CCDIN 2 1.00 GND 3 AIN1 4 0.10 GND 5 AIN2 6 0.01 3 4 5 6 7 8 9 10 NUMBER OF TIME CONSTANTS I.C. 9 I.C. 10 16 GND 15 VDD 14 REFBIAS 13 REF+ GND 7 I.C. 8 24 GND 23 VDD 22 BLKSAMP 21 VIDSAMP
MAX1101
20 LOAD 19 DATA 18 SCLK 17 MODE
Figure 13. Black Level Error vs. CEXT Time Constant at Maximum PGA Gain (1mV/bit)
REFGND 11 REF- 12
Bypassing and Layout Considerations
Solder the MAX1101 to a multilayer board (two or more layers) where the layer immediately beneath the device is a ground plane. Connect the VDD pins together at the MAX1101. Connect all ground pins together at the device. Bypass VDD to ground with at least a 0.1F ceramic capacitor. If larger capacitors are used, tantalum is satisfactory.
SO
___________________Chip Information
TRANSISTOR COUNT: 3430
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11
Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA MAX1101
________________________________________________________Package Information
SOICW.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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